Increasing numbers of semiconductor devices, such as individual memory cells, are being created on a single chip. As a result, dimensions of the devices continue to shrink. Shrinking device dimensions can increase the difficulty of ensuring proper alignment over an adequate functional area of the structures included in the semiconductor devices.
For example, a merged isolation node trench (MINT) cell is illustrated in FIG. 1. The MINT cell illustrated in FIG. 1 includes a planar transfer device. The device shown in FIG. 1 includes a deep trench capacitor 1 a shallow trench isolation region 2 used to define the active area, a bit line contact (CB) 3, a word line (WL) 5, or transfer device gate, gate oxide 7 and N+ source/drain regions 9 and 11. In the structure illustrated in FIG. 1, a buried strap 12 connects the deep trench capacitor storage trench node 1 to the source/drain diffusion 11 of the transfer device. In a MINT cell, MINT buried strap resistance may be a function of the overlap of the deep trench 1 and the shallow trench isolation region 2 of the memory cell.